Construct · 1 fields · 1 citations

logical effort: a standalone construct

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Electronics

delay model for CMOS logic that expresses each gate's delay through its logical effort, electrical effort and parasitic delay, used to size gates along a path.

In electronics, logical effort refers to delay model for CMOS logic that expresses each gate's delay through its logical effort, electrical effort and parasitic delay, used to size gates along a path. This meaning comes from Sutherland (1999) in Logical effort: designing fast CMOS circuits.[1]

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Nearby constructs

effort2 fields · 2 citationsjingle · one word, two constructs gate5 fields · 6 citationsjingle · one word, five constructs model3 fields · 3 citationsjingle · one word, three constructs

References

Sutherland, I. E. (1999). Logical effort: designing fast CMOS circuits. Morgan Kaufmann Publishers. ISBN 9781558605572

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