Construct · 1 fields · 2 citations
One name. One construct. A landmark on the map.
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Latch-up is a failure mode of CMOS integrated circuits in which the parasitic bipolar transistors inherent in the n- and p-type regions form a four-layer thyristor that, once triggered, switches into a self-sustaining low-impedance state shorting the supply to ground. Gregory and Shafer's 1973 Latch-up in CMOS integrated circuits identified the mechanism, and Estreich and Dutton's 1982 modeling work quantified the trigger conditions and holding behaviour. The referent is a parasitic regenerative conduction state that can destroy a chip unless current is removed, characterised by its trigger and holding currents and designed against through guard rings and substrate contacts.[1][2]
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